Product Core Brief
- Model: MVME104
- Brand: Motorola Computer Group
- Series: MVME10x VMEbus single board computers
- Core Function: 68010-based VME master/slave processor with serial/parallel I/O
- Product Type: VMEbus SBC (A24/D16 master/slave)
- Key Specs: MC68010 @ 10 MHz | 512 KB DRAM | 1 × RS-232 | 1 × Centronics parallel
- Condition: New Original (New Surplus) — verify jumper settings and burn-in test
Product Introduction
Motorola MVME104 provides MC68010 processing at 10 MHz on the VMEbus with 512 KB DRAM and basic I/O for embedded control and test systems. It operates as A24/D16 master/slave on the VME backplane while managing RS-232 serial and Centronics parallel communications through onboard MC68450 DMA and MC68901 MFP.
The board targets early VME applications including RTU controllers, process monitors, and protocol converters where 68000-family code runs on cost-sensitive single-board platforms. Four EPROM sockets hold monitor/boot code; DRAM supports RAM disk or application data space.
Frequently Asked Questions
Q: Does the MVME104 support hot-swapping in a VME chassis?
A: VMEbus standards prohibit live insertion; power down the entire crate before installing the MVME104. The 2.5 A @ 5 VDC draw requires verifying crate power capacity, and bus arbitration asserts SYSFAIL during swaps—measure all three rails post-install and scope VME signals before attempting boot.
Q: Is the MVME104 obsolete, and what migration paths exist?
A: Obsolete since early 1990s; Motorola’s MVME10x series gave way to MVME110/147 (68020/30) then PowerPC boards like MVME160/260. All require code recompilation from 68010 to PPC ISA; pin-compatible VME SBCs from Heurikon or Force Computers offer hardware drop-ins but different firmware loaders.
Q: Will I lose application code or configuration when replacing the MVME104?
A: Code stored in EPROM or DRAM clears only if battery fails on RTC SRAM; board swap preserves neither unless backed externally. Common error is undocumented jumper settings (RAM timing, serial flow control)—photograph JP1-JP10 positions, dump all four ROMs with EPROM programmer, match DRAM population before new board powers up.
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